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Understanding About CMOS Fabrication Technology

August 2, 2014 by Tarun Agarwal 26 Comments

CMOS Technology

CMOS Fabrication

In early 1960’s the semiconductor manufacturing process was initiated from Texas and in 1963 CMOS or complementary metal oxide semiconductor was patented by Frank Wanlass. Integrated circuits are manufactured by utilizing the semiconductor device fabrication process. These ICs are major components of every electrical and electronic devices which we use in our daily life. Many complex and simple electronic circuits are being designed on a wafer made of semiconductor compounds and mostly silicon by using different fabrication steps.

The complementary of the Commodore Semiconductor Group (CSG) or Metal Oxide Semiconductor (MOS) is called as CMOS technology. This technology is used in developing the microprocessors, microcontrollers, digital logic circuits and many other integrated circuits. It facilitates low- power dissipation and high-packing density with very less noise margin. It is mostly used to build digital circuitry.

20 Steps of CMOS Fabrication Process

The CMOS can be fabricated using different processes such as:

  • N-well process for CMOS fabrication
  • P-well process
  • Twin tub-CMOS-fabrication process

The fabrication of CMOS can be done by following the below shown twenty steps, by which CMOS can be obtained by integrating both the NMOS and PMOS transistors on the same chip substrate. For integrating these NMOS and PMOS devices on the same chip, special regions called as wells or tubs are required in which semiconductor type and substrate type are opposite to each other.

A P-well has to be created on a N-substrate or N-well has to be created on a P-substrate. In this article, the fabrication of CMOS is described using the P-substrate, in which the NMOS transistor is fabricated on a P-type substrate and the PMOS transistor is fabricated in N-well.

The fabrication process involves twenty steps, which are  as follows:

Step1: Substrate

Primarily, start the process with a P-substrate.

Step2: Oxidation

The oxidation process is done by using high-purity oxygen and hydrogen, which are exposed in an oxidation furnace approximately at 1000 degree centigrade.

Step3: Photoresist

A light-sensitive polymer that softens whenever exposed to light is called as Photoresist layer. It is formed.


Step4: Masking

The photoresist is exposed to UV rays through the N-well mask


Step5: Photoresist removal

A part of the photoresist layer is removed by treating the wafer with the basic or acidic solution.

Step6: Removal of SiO2 using acid etching

The SiO2 oxidation layer is removed through the open area made by  the removal of photoresist using hydrofluoric acid.

Step7: Removal of photoresist

The entire photoresist layer is stripped off, as shown in the below figure.


Step8: Formation of the N-well

By using ion implantation or diffusion process N-well is formed.


Step9: Removal of SiO2

Using the hydrofluoric acid, the remaining SiO2 is removed.


Step10: Deposition of polysilicon

Chemical Vapor Deposition (CVD) process is used to deposit a very thin layer of gate oxide.


Step11: Removing  the  layer barring a small area for the Gates

Except the two small regions required for forming the Gates of NMOS and PMOS,  the remaining layer is stripped off.

Step12: Oxidation process

Next, an oxidation layer is formed on this layer with two small regions for the formation of the gate terminals of NMOS and PMOS.


Step13: Masking and N-diffusion

By using the masking process small gaps are made for the purpose of N-diffusion.

The n-type (n+) dopants are diffused or ion implanted, and the three n+ are formed for the formation of the terminals of NMOS.


Step14: Oxide stripping

The remaining oxidation layer is stripped off.

Step15: P-diffusion

Similar to the above N-diffusion process, the P-diffusion regions are diffused to form the terminals of the PMOS.

Step16: Thick field oxide

A thick-field oxide is formed in all regions except the terminals of the PMOS and NMOS.


Step17: Metallization

Aluminum is sputtered on the whole wafer.

Step18: Removal of excess metal

The excess metal is removed from the wafer layer.

Step19: Terminals

The terminals of the PMOS and NMOS are made from respective gaps.

Step20: Assigning the names of the terminals of the NMOS and PMOS

Fabircation of CMOS using P-well process

Among all the fabrication processes of the CMOS, N-well process is mostly used for the fabrication of the CMOS. P-well process is almost similar to the N-well. But the only difference in p-well process is that it consists of a main N-substrate and, thus, P-wells itself acts as substrate for  the N-devices.

Twin tub-CMOS Fabrication Process

In this process, separate optimization of the n-type and p-type transistors will be provided. The independent optimization of Vt, body effect and gain of the P-devices, N-devices can be made possible with this process.

Different steps of the fabrication of the CMOS using the twintub process are as follows:

  • Lightly doped n+ or p+ substrate is taken and, to protect the latch up, epitaxial layer is used.
  • The high-purity controlled thickness of  the layers of silicon are grown with exact dopant concentrations.
  • The dopant and its concentration in Silicon are used to determine electrical properties.
  • Formation of the tub
  • Thin oxide construction
  • Implantation of the source and drain
  • Cuts for making contacts
  • Metallization

By using the above steps we can fabricate CMOS using twintub process method.

CMOS Logic Gates

  • The P-type and N-type transistors are called as fundamental building blocks of CMOS circuits.
  • If the input voltage is low, then P-type MOSFET acts as closed switch and, if the input voltage is high, then the P-type MOSFET acts as open switch.
  • If the input voltage is high, then the N-type MOSFET acts as a closed switch and, if input the voltage is low, then the N-type MOSFET acts as an open switch.
  • Combining the P-type and N-type MOSFETs without any conduction path between the supply voltage and the ground is the basic idea behind developing the CMOS technology.
  • With this combination, very little energy is consumed by the CMOS circuits.

CMOS Inverter

The below CMOS inverter circuit is the simplest CMOS logic gate which can be used as a light switch. If the input voltage is low (0V), then the transistor (P-type) T1 conducts (switch closed) while the transistor T2 doesn’t conduct (switch open). Hence, the output of the circuit will be equal to the supply voltage (5V).

Similarly, if the input voltage is high (5V), then the transistor (N-type) T2 conducts (switch close) while the transistor T1 doesn’t conduct (switch open). Hence, the output of the circuit will be low (0V).

The above truth table shows the function of the CMOS inverter circuit and, from the table, we can observe that the output of the circuit is the inverse of the input.

Everytime whether the input is low or high, one of the two transistors conducts such that no current flows from the supply to ground.

For detailed information regarding the fabrication process of CMOS, which includes P-type and twintub processes and also advanced-fabrication process such as combination of Bipolar and CMOS ( BiCMOS fabrication), please post your ideas and queries by commenting below.

Filed Under: Electronics, Others

About Tarun Agarwal

Tarun Agarwal is the Chief Customer Support Officer at Edgefx Technologies Pvt Ltd. He has 8 years of experience in Customer Support, Operations and Administration.

Comments

  1. SUHAILA KM says

    August 5, 2014 at 11:48 am

    sir iam from kerala..and i would like to knopw more about the project car security system using gsm….and plz help me to get the source code and circuit diagram..

    Reply
    • Tarun Agarwal says

      August 5, 2014 at 2:32 pm

      Hi SUHAILA KM,

      The circuit diagram, code, component list, documentation and other information could be shared with you when you purchase the project.

      Please check our model no. 154 for your exact requirement.

      Please follow the link: http://www.edgefxkits.com/theft-intimation-of-the-vehicle-over-gsm-by-sms-with-user-programable-number-features-to-owner-who-can-stop-the-engine-remotely

      You can download project abstract and seminar presentation from our website http://www.edgefxkits.com
      Please check the website for complete details in the kit content section and go through the FAQ for details.
      Please get back to us at info@edgefxkits.in or call the undersigned on 0 99591 78000 or our toll free no. 1800 108 7475 for clarifications/personal counseling.

      Thanks and Regards

      Suvarna
      Mobile: +91 9959178000

      Reply
  2. Rajalakshmi says

    February 22, 2016 at 8:26 pm

    Sir I am from Coimbatore.I would like to know about advanced technology used in CMOS fabrication

    Reply
    • Tarun Agarwal says

      February 23, 2016 at 5:50 pm

      Hi Rajalakshmi,
      Sorry,we don’t deal with CMOS technology.
      Only we deal with Embedded platform.
      For more details please Mr.Tarun Agarwal on +91-9908208883.

      Reply
  3. Vaibhavi Rocha says

    May 12, 2016 at 7:27 pm

    thank you so much.you made everything so easy!!!!!

    Reply
    • Tarun Agarwal says

      May 13, 2016 at 4:48 pm

      Hi Vaibhavi

      Thanks for your compliment
      once again please visit our website http://www.edgefxkits.com/

      For more details please contact Mr. Tarun Aggarwal on +91 9908208883

      Reply
  4. SATWIK GALI says

    July 6, 2016 at 2:54 am

    Hello Sir, In the final step of CMOS fabrication, apart from gate, drain and source, you mentioned ‘B’. I would like to know what that means. Thank you

    Reply
    • Tarun Agarwal says

      July 11, 2016 at 10:17 am

      Hi Satwik Gali
      As per your query B determine Bird’s eye view of a stack layers
      And once again please visit our web site http://www.edgefxkits.com/

      For more details please contact our customer support on +91 9959178000

      Reply
  5. sowmiya says

    September 30, 2016 at 5:25 pm

    Hello. what is the purpose of adding thick field oxide in step 16? what is the need for it?

    Reply
    • Tarun Agarwal says

      October 1, 2016 at 6:10 pm

      Hi Sowmiya
      The thick field oxide layer is used to cover the chip
      And once again please visit our website http://www.edgefxkits.com/

      For furthermore details please contact to sathish on +91 8885507011 or you can email us on info@edgefxkits.in

      Reply
  6. Hania Irshad says

    November 11, 2016 at 7:46 am

    this was really helpful !! thankyou.

    Reply
    • Tarun Agarwal says

      November 11, 2016 at 6:29 pm

      Hi Hania Irshad
      Thank you so much
      And once again please visit our website http://www.edgefxkits.com/

      For further more details please contact to Mr. Sathish on +91 8885507011 or you cane email us on info@edgefxkits.in

      Reply
  7. Joe Vinil says

    November 25, 2016 at 11:02 am

    Does N-well and P-well has the same process?

    Reply
    • Tarun Agarwal says

      November 26, 2016 at 3:21 pm

      Hi Joe Vinil
      As per your query please follow the below links
      https://www.elprocus.com/difference-between-npn-and-pnp-transistor/
      https://www.elprocus.com/simple-transistor-tester-circuit/
      And visit our website for domestic http://www.edgefxkits.com/ and for international http://www.efxkits.com/

      For furthermore details please contact to Mr. Sathish on +91 8885507011 or you can email us on info@edgefxkits.in

      Reply
  8. Parth Rastogi says

    February 12, 2017 at 10:11 am

    Sir,
    I saw the project of car security system which was awesome. I am willing to make this project as i am a student of B.Tech 3rd yr (ECE).
    So i request you to please help me by sending the code to the given mail id.
    Thank you.

    Reply
    • Tarun Agarwal says

      July 5, 2017 at 4:35 pm

      Hi Parth Rastogi
      As per your query, I can suggest you that, we provide you DIY (do-it-yourself) kits. With these kits, you can get practical knowledge. once you purchase the project from our website http://www.edgefxkits.com/, you will be provided with all support documents, components, soldering kit, and video tutorials.
      please visit our domestic website http://www.edgefxkits.com/
      For more details please contact to Mr. Sathish on +91 8885507011 (toll-free) or you can email us on info@edgefxkits.in

      Reply
  9. Parth Rastogi says

    February 12, 2017 at 10:13 am

    Sir ,
    I forgot to mention the model no.
    Model no. 154

    Reply
    • Tarun Agarwal says

      July 5, 2017 at 4:35 pm

      Hi Parth Rastogi
      As per your query, I can suggest you that, we provide you DIY (do-it-yourself) kits. With these kits, you can get practical knowledge. once you purchase the project from our website http://www.edgefxkits.com/, you will be provided with all support documents, components, soldering kit, and video tutorials.
      please visit our domestic website http://www.edgefxkits.com/
      For more details please contact to Mr. Sathish on +91 8885507011 (toll-free) or you can email us on info@edgefxkits.in

      Reply
  10. arvind kumar says

    April 5, 2017 at 3:23 pm

    initialy i was not aware much about the fabrication but after seeing your notes all doubt are clear easly… thanks..

    Reply
    • Tarun Agarwal says

      July 5, 2017 at 4:36 pm

      Hi arvind kumar
      Thank you very much for telling me how much you have enjoyed reading my column
      And once again please visit our domestic website http://www.edgefxkits.com/
      For more details please contact to Mr. Sathish on +91 8885507011 or you can email us on info@edgefxkits.in

      Reply
  11. Mayur Madhavrao Bhandarkumthe says

    September 7, 2017 at 2:15 pm

    Hi Sir,
    That was really a good and simple explanation.I loved it.I just had 1 question.Why do people start with P-substarte as base wafer ,what advantage does it provide over n-substarte.
    Thanks & Regards,
    Mayur

    Reply
    • Tarun Agarwal says

      September 13, 2017 at 3:59 pm

      It is because of the convention that the power supply is positive with respect to common (ground). It would be entirely possible to fabricate it with an N type substrate and P wells for a negative power supply, but charge carriers are less mobile in P-type so that would result in longer propagation delays.

      An N to P junction is reverse biased when the P is at a lower voltage than the N. That allows simple isolation for NMOS transistors. PMOS transistors are fabricated in a N type well for the same reason. In the diagram below, the contact B on the right is the positive power supply, the B on the left is the common (ground). The entire P substrate is at ground potential.
      Please visit our domestic website http://www.edgefxkits.com/
      For more details please contact to Mr. Sathish on +91 8885507011 or you can email us on info@edgefxkits.in

      Reply
  12. Anirudh khatwani says

    November 4, 2017 at 1:45 pm

    Execellent .

    Reply
    • Tarun Agarwal says

      November 15, 2017 at 5:28 pm

      Hi ANIRUDH
      THANK YOU SO MUCH FOR YOUR FAVOURABLE REPLY.
      PLEASE VISIT OUR WEBSITE http://WWW.EDGEFXKITS.COM

      Reply
  13. Sadegh M says

    December 25, 2017 at 9:49 pm

    Hi
    this was really helpful for me! thank you so much!
    can you help me about BiCMOS fabrication Technology?
    The contents of this website ” http://www.elprocus.com” were not so detailed about BiCMOS fabrication.

    Reply
    • Tarun Agarwal says

      December 26, 2017 at 10:30 am

      Hi Sadegh,
      Thank you so much for your feedback Please refer the following link for your requirement
      https://www.elprocus.com/bicmos-technology-fabrication-and-applications/
      For any technical information visit https://www.elprocus.com
      please visit our domestic website http://www.edgefxkits.com/
      For more details please contact to Sathish on +91 8885507011 or you can email us on info@edgefxkits.in

      Reply

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